1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving a four-mask process, thereby resolving a problem of stitch lines.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) device includes an upper substrate, a lower substrate, and an interposed liquid crystal therebetween. The upper and lower substrates respectively have electrodes opposing to each other. When an electric field is applied between the electrodes of the upper and lower substrates, molecules of the liquid crystal are aligned according to the electric field. By controlling the electric field, the liquid crystal display device provides various transmittances for rays of light to display images.
By now, an active matrix LCD (AM LCD) device is the most popular because of its high resolution and superiority in displaying moving video data. A typical AM LCD device has a plurality of switching elements and pixel electrodes, which are arranged in an array matrix on the lower substrate. Therefore, the lower substrate of the AM LCD device is alternatively referred as an array substrate.
On the upper substrate of the AM LCD device, a common electrode made of a transparent conductive material is usually formed. In case of a color LCD device, a color filter is further formed between the upper substrate and the common electrode of the upper substrate.
The above-mentioned lower substrate and the upper substrate are attached together with each other using a sealant therebetween. A liquid crystal is then interposed into a cell gap formed between the upper and lower substrates.
Because the pixel and common electrodes, as mentioned above, are respectively positioned on the lower and upper substrates, the electric field induced therebetween is perpendicular to the lower and upper substrates. The above-mentioned liquid crystal display device has high transmittance and aperture ratio. In addition, since the common electrode on the upper substrate serves as a ground, static electricity destroying the liquid crystal display device is eliminated.
At this point, there exist various intervals around the pixel electrode or other elements. If rays of light pass through the intervals, abnormal images may be displayed. To avoid a leakage of light, the upper substrate further includes a black matrix. The black matrix shields the intervals, thereby preventing rays of light from passing through the intervals.
Five or six masks were conventionally used in a masking step for fabricating the array substrate for an LCD device. Since the masking step includes a plurality of sub-steps including cleaning, depositing, baking, etching, and the like, if one masking step can be reduced, fabrication time and cost greatly decrease. Therefore, a research for decreasing the total number of masks has been actively performed such that four masks are now using in fabricating the LCD device.
Referring to FIGS. 1 and 2, an array substrate is fabricated by applying a conventional four-mask processing. FIG. 1 is a plane view illustrating the array substrate while FIG. 2 is a cross-sectional view taken along the line II—II of FIG. 1.
As shown, a gate line 21 is disposed on the array substrate 10, and a gate electrode 22 protrudes from the gate line 21 in the direction perpendicular to the gate line 21. A gate insulating layer 30 is disposed to cover the gate line 21 including the gate electrode 22. An undoped amorphous silicon layer 41 and a doped amorphous silicon layer 52 are sequentially are disposed on the gate insulating layer 30. The undoped amorphous silicon layer 41 disposed over the gate line 22 serves as an active layer (hereinafter, the reference numeral 41) while the doped amorphous silicon layer 52 disposed on the active layer 41 serves as an ohmic contact layer (hereinafter, the reference numeral 52).
On the ohmic contact layer 52, a data line 61 perpendicularly crossing the gateline 21, a source electrode 62 and a drain electrode 63 are disposed thereon. The source electrode 62 protrudes from the data line 61 while the drain electrode 63 is spaced apart from the source electrode 62 with the gate electrode 22 centering on therebetween.
The gate electrode 22, the source electrode 62, the drain electrode 63, and the active layer 41 collectively define a thin film transistor “T”, which serves as a switching element of the LCD device. Further, a passivation layer 71 is formed to cover all of the data line 61, the source electrode 62, and the drain electrode 63. The passivation layer 71 has the same shape as the active layer 41 in the plane view of FIG. 1. In a pixel region “P” defined by the crossing gate and data lines 21 and 61, a pixel electrode 81 formed of a transparent conductive material is disposed thereon.
As previously mentioned, a black matrix formed on a color filter substrate is used for preventing rays of light from leaking through various intervals around the pixel electrode 81. FIG. 3 shows the black matrix 90, which covers the above-mentioned electrical lines and electrodes except for the pixel electrode 81.
With reference to FIGS. 4A to 4C and FIG. 2, conventional process steps for fabricating the above-mentioned array substrate is explained hereinafter. These process steps have been suggested in U.S. patent application Ser. No. 09/885,527.
In FIG. 4A, a first metal layer is deposited on the array substrate 10 and patterned using a first mask to form the gate electrode 22 and the gate line (not shown).
In FIG. 4B, the gate insulating layer 30, an amorphous silicon layer 40, a doped amorphous silicon layer, and a second metal layer are sequentially deposited on the array substrate 10. The second metal layer and the doped amorphous silicon layer are subsequently patterned using a second mask such that the data line 61, the source electrode 62, the drain electrode 63, and the ohmic contact layer 52 are formed. A portion 52a (shown in FIG. 6A) of the doped amorphous silicon layer below the data line 61 is protected from etching processes, thereby remaining even after the etching processes. Sputtering is preferably used for depositing the second metal layer, and photolithography is preferably used for patterning in the above processes.
In FIG. 4C, silicon nitride or silicon oxide is deposited on the array substrate 10 and then patterned together with the amorphous silicon layer (shown in the reference numeral 40 of FIG. 4B) using a third mask. As a result, the passivation layer 71 and the active layer 41 are formed thereon. The passivation layer 71 covers the data line 61, the source electrode 62, and the drain electrode 63. The side edge of the drain electrode 63 is however exposed out of the passivation layer 71.
As shown in FIG. 2, a transparent conductive material is deposited on the array substrate 10 and patterned using a fourth mask such that the pixel electrode 81 is formed thereon. The pixel electrode 81 contacts the exposed side edge of the drain electrode 63. Further, the pixel electrode 81 overlaps a portion of the previous gate line 21a that precedes the gate line 21 defining the pixel region “P”.
As explained above, because only four masks are used in fabricating the array substrate, a fabrication cost can be reduced.
An exposure apparatus is used for photolithography of the above-explained method. The exposure apparatus can expose only a specific area at one time. Therefore, if a substrate to be exposed is much larger than the specific area of the exposure apparatus, a step-and-repeat exposure process is applied. In the step-and-repeat exposure process, portions of the substrate are sequentially exposed to light until the overall surface of the substrate is exposed to light.
FIG. 5 and FIGS. 6A to 6C show the steps of forming the passivation layer 71 by applying the step-and repeat exposure process.
In FIG. 6A, after an insulating layer 70 is formed to cover the second metal layer including the data line 61, a photoresist 100 is deposited on the insulating layer 70. The photoresist 100 is repeatedly exposed to light by applying the step-and-repeat exposure process. During the step-and-repeat exposure, first to fourth regions “A” to “D” of the substrate shown in FIG. 5 are sequentially exposed to light.
After the exposure is completed, the photoresist 100 is developed and etched such that it is patterned to have first to third photoresist portions 100a, 100b, and 100c, as shown in FIG. 6B. The first photoresist portion 100ais thicker than the second photoresist portion 100b. The third photoresist portion 100c is shown as an open hole exposing a portion of the insulating layer 70.
Various thickness of the patterned photoresist 100 can be achieved by controlling an exposing time with respect to desired portions. The first photoresist portion 100a covers the second metal layer including the data line 61 and is shielded from rays of light during the exposure. The third photoresist portion 100c covers regions around the broken lines of FIG. 5 and is exposed twice to light. The second photoresist portion 100b covers the other regions except for the second metal layer and the boundary lines, and is exposed to light for just one time.
After the developing and etching processes, the first photoresist portion 100a has no change in its thickness, whereas the third photoresist portion 100c is totally removed to be an open hole. Further, the second photoresist portion 100b has a smaller thickness than the first photoresist portion 100a. 
After the photoresist 100 is patterned, the first and second photoresist patterns 100a and 100b are etched together with various layers including the insulating layer 70 and the amorphous silicon layer 40. A dry etching is usually selected for the above-mentioned etching process. After the dry etching is finished, the first photoresist portion 100a having the largest thickness still remains and has a decreased thickness. Therefore, portions of the insulating layer 70 below the first photoresist portion 100a are protected from the etching.
However, portions of the insulating layer 70, the amorphous silicon layer 40, and the gate insulating layer 30 that correspond to the third portion 100c are removed in the process. Specifically, the removed portion of the gate insulating layer 30 is referred to as a stitch line “S” (shown in FIG. 6C). In addition, portions of the insulating layer 70 and the amorphous silicon layer 40 below the second photoresist portion 100b are removed during the etching process. After the above-mentioned etching is completed, a residual portion of the photoresist 100 is further removed via an additional processing such as ashing or cleaning.
In FIG. 6C, the passivation layer 71 and the active layer 41 are formed. The passivation layer 71 and the active layer 41 are respectively the insulating layer 70 (shown in FIG. 6B) and the amorphous silicon layer 40 (shown in FIG. 6B) disposed below the first photoresist portion 100 (shown in FIG. 6B). The stitch lines “S” are conventionally formed at the pixel region “P” (shown in FIG. 5), thereby causing a problem in display quality of the conventional LCD device.
As explained above, when the step-and-repeat exposure process is used for forming the passivation layer 71, the stitch lines “S” are conventionally formed at the pixel region “P”. Since the stitch line “S” is formed at the pixel region “P” (shown in FIG. 1) serving as a portion of the display area of the LCD device, a stain may be seen on the display area.
FIG. 7 illustrates another problem caused by the conventional step-and-repeat exposure process. In case of applying the step-and-repeat exposure process to pattern the photoresist, the shape of the previously exposed portion may not match that of a later exposed portion since portions of the photoresist are exposed at different times.
After the photoresist is patterned, it has a different shape from the desired one. Since the patterned photoresist is used for forming the passivation layer, the passivation layer cannot be formed to have a desired shape. For example, as shown in FIG. 7, a first portion 71a and a second portion 71b of the passivation layer 71 may not coincide with each other such that the passivation layer 71 is crooked. In such a case, the first portion 71a at the first region “A” and the second portion 71b at the second region “B” exhibit different distances measured from the pixel electrode 81. As a result, the above-mentioned distance variation between the pixel electrode 81 and the passivation layer 71 causes a capacitance variation between the pixel electrode 81 and the data line 61 with respect to different regions.